Power converters and associated methods of control

ABSTRACT

SIMO power converters and associated methods of control are disclosed herein. In one embodiment, a method of converting a signal input signal into multiple output signals includes supplying power to a plurality of output terminals based on a signal input signal, detecting a voltage at individual output terminals, determining an arithmetic relationship between the detected voltages of the output terminals, and adjusting the power supplied to the plurality of output terminals based at least in part on the determined arithmetic relationship between the detected voltages of the output terminals.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims priority to Chinese Application No.200810045583.4, filed on Jul. 17, 2008, and incorporated herein byreference in its entirety.

TECHNICAL FIELD

The present disclosure relates to power converters; and moreparticularly, to single inductor multiple output (SIMO) powerconverters.

BACKGROUND

Switching circuits are widely utilized in a number of power supplyapplications. Three basic topologies of such switching circuits include(1) a buck converter, (2) a boost converter, and (3) a buck-boostconverter. However, when multiple output are required, SIMO powerconverters can reduce cost and size of the device because only oneinductor is used.

Conventional SIMO converters typically utilize a “priority” controlscheme. According to the “priority” control scheme, when a SIMOconverter detects that the voltage of one output is dropping too low,the SIMO converter would cut off power delivery to other output duringsubsequent cycles to compensate the output with the low voltage. Thiscontrol scheme can cause high-ripple in the cut-off output because of alack of power supply during the subsequent cycles. Other SIMO powerconverter techniques use digital control which are complicated andexpensive. Accordingly, there is a need for efficient and cost-effectivecontrol circuits for SIMO power converters.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a SIMO circuit in accordance withembodiments of the disclosure.

FIG. 2A depicts waveforms of an inductor current and switching signalsin the SIMO circuit shown in FIG. 1 in one mode of operation.

FIG. 2B depicts waveforms of an inductor current and switching signalsin the SIMO circuit shown in FIG. 1 in another mode of operation.

FIG. 2C depicts waveforms of an inductor current and switching signalsin the SIMO circuit shown in FIG. 1 in yet another mode of operation.

FIG. 2D depicts waveforms of an inductor current and switching signalsin the SIMO circuit shown in FIG. 1 in a further mode of operation.

FIG. 3 is a schematic diagram of a control circuit useful in the SIMOcircuit shown in FIG. 1 in accordance with embodiments of thedisclosure.

FIG. 4A depicts waveforms of the control circuit shown in FIG. 3 whilethe SIMO circuit shown in FIG. 1 is in one mode of operation.

FIG. 4B depicts waveforms of the control circuit shown in FIG. 3 whilethe SIMO circuit shown in FIG. 1 is in another mode of operation.

DETAILED DESCRIPTION

Specific details of several embodiments of the disclosure are describedbelow with reference to power converters and associated methods ofcontrol. Moreover, several other embodiments of the converters may havedifferent configurations, components, or procedures than those describedin this section. A person of ordinary skill in the art, therefore, willaccordingly understand that the converters and the associated methods ofoperation may have other embodiments with additional elements, or theinvention may have other embodiments without several of the elementsshown and described below with reference to FIGS. 1-4B.

FIG. 1 is a schematic diagram of a SIMO circuit in accordance withembodiments of the disclosure. As shown in FIG. 1, the SIMO circuitcomprises an input V_(IN), two output V_(P) and V_(N), an inductor L,two capacitors C₁ and C₂, two switches M₁ and M₂, two diodes D₁ and D₂interconnected to one another. The individual control gate of switchesM₁ and M₂ are coupled to a control circuit, an example of which isdiscussed in more detail below with reference to FIG. 3.

In certain embodiments, the switches M₁ and M₂ can individually includean N-channel MOSFET. In other embodiments, the switches M₁ and M₂ caninclude P-channel MOSFET or other suitable types of MOSFET. In furtherembodiments, the switches M₁ and M₂ can also include a transistor, anIGBT, and/or other suitable switching devices. In yet furtherembodiments, the diodes D₁ and D₂ can be replaced by suitable types ofswitches. Even though only two output are illustrated in FIG. 1, theSIMO circuit can also include three, four, or any other desired numberof output. In further embodiments, the SIMO circuit may have otherdesired SIMO topologies.

In operation, the switch M₁ and the diode D₂ are turned oncomplementarily, while the switch M₂ and the diode D₁ are turned oncomplementarily. In certain embodiments, one switching cycle of the SIMOcircuit may include three sub-periods when the system is in a continuouscurrent mode (CCM): 0˜t₀, t₀˜t₁, t₁˜T, as shown in FIGS. 2A and 2B. Inother embodiments, the switching cycle of the SIMO circuit may includeother switching periods.

During a first sub-period 0˜t₀, the switches M₁ and M₂ are turned onsimultaneously while the diodes D₁ and D₂ are turned off. The inputV_(IN), the switch M₁, the inductor L, and the switch M₂ form a currentloop. The inductor current I_(L) is increased linearly at a slope ofV_(IN)/L as the input V_(IN) is supplied to the inductor L.

There may be two operating scenarios during a second sub-period t₀˜t₁.According to operating scenario 1, the switch M₁ is turned on, the diodeD₁ is freewheeling, and the switch M₂ and the diode D₂ are off. Then theinput V_(IN), the switch M₁ , the inductor L, the diode D₁, and thecapacitor C₁ form a current loop. As shown in FIG. 2A, the inductorcurrent I_(L) declines linearly at a slope of (V_(P)−V_(IN))/L, theinput V_(IN) and the inductor L are supplied to the capacitor C₁ and theload, thus providing the output V_(P).

According to operating scenario 2, the switch M₂ is turned on, the diodeD₂ is freewheeling, and the switch M₁ and the diode D₁ are off. Then theinductor L, the switch M₂, the capacitor C₂, and the diode D₂ form acurrent loop. As shown in FIG. 2B, the inductor current I_(L) declineslinearly at a slope of V_(N)/L while the inductor L supplies power tothe capacitor C₂ and the load, thus providing the negative output V_(N).

During a third sub-period t₁˜T, the switches M₁ and M₂ are turned offsimultaneously, and diodes D₁ and D₂ are freewheeling. The inductor L,the diode D₁, the capacitor C₁, the diode D₂, and the capacitor C₂ forma current loop. The inductor current I_(L) declines linearly at a slopeof (V_(P)−V_(N))I_(L) while the inductor L supplies power to thecapacitors C₁, C₂ and the load.

FIG. 3 is a schematic diagram of a control circuit useful in the SIMOcircuit shown in FIG. 1 in accordance with embodiments of thedisclosure. As shown in FIG. 3, the control circuit can include twocontrol loops to control the operation of the switches M₁ and M₂ (FIG.1). In the illustrated embodiment, control loop 1 controls a peakcurrent of the inductor current, i.e., a length of the first sub-period,while control loop 2 controls a length of the second sub-period, i.e.,the duty-cycle difference between the two switches M₁ and M₂ in the SIMOcircuit. Control loop 2 also determines which operating scenario to useduring the second sub-period.

Control loop 1 comprises a peak-current control value setting circuit 1,an adder 2 (i.e., adder A₂), a first comparator 3 (i.e., comparator U₃),a slope signal generator 4, a first logic circuit 5, and a second logiccircuit 6. In the illustrated embodiment, the peak-current control valuesetting circuit I comprises two operational amplifiers U₀, U₁, and afirst calculator 11 (e.g., a an adder A₀). The slope signal generator 4includes an oscillator OSC. The first logic circuit 5 includes a RSflip-flop U₈, and the second logic circuit 6 comprises a first OR gateU₆, a second OR gate U₇, a first switch S₁, a second switch S₂, a firstresistor R₁, and a second resistor R₂ interconnected as shown in FIG. 3.

Control loop 2 comprises a switch duty-cycle difference control circuit7 and the second logic circuit 6. In one embodiment, the switchduty-cycle difference control circuit 7 comprises an adder (i.e., adderA₁), a second operational amplifier U₂, an absolute value circuit ABS, asecond comparator U₄, a third comparator U₅, a current source I_(S), acapacitor C₀, and a switch S₃. The non-inverting input terminal of theoperational amplifier U₀ receives a reference voltage V_(ref—P), and theinverting input terminal of the operational amplifier U₀ receives asensed signal V_(p′) of the system output V_(P). The operationalamplifier U₀ amplifies the difference between V_(p′) and the referencevoltage V_(ref—p) and supplies the amplified result to one inputterminal of the adder A₀.

The inverting input terminal of the operational amplifier U₁ receives areference voltage V_(ref—N) while the non-inverting input terminal ofthe operational amplifier U₁ receives another sensed signal V_(N′) ofthe system output V_(N). The operational amplifier U₁ amplifies thedifference between V_(N′) and the reference voltage V_(ref—N) andsupplies the result to the other input terminal of the adder A₀. Theadder A₀ adds the output of the operational amplifiers U₀ and U₁, andsends an output to the inverting input terminal of the third comparatorU₃. One input terminal of the adder A₂ receives a signal I_(M), which isa sensed current flowing through the switch M₂.

Without being bound by theory, it is believed that I_(M) is equal to theinductor current I_(L) of the SIMO circuit during the first sub-period0˜t₀. Therefore, the peak value of the inductor current I_(L) is thepeak value of I_(M). It is also believed that the input terminal of theadder A₂ that receives the signal I_(M) can also receive the inductorcurrent I_(L). The other input terminal of the adder A₂ receives oneoutput of the oscillator OSC which can include a saw-tooth signal. Theadder A₂ adds I_(M) with the saw-tooth signal from the oscillator OSC,and sends its output to the non-inverting input terminal of the thirdcomparator U₃.

The output terminal of the comparator U₃ is coupled to the resetterminal R of the RS flip-flop U₈ and the control terminal of the switchS₃. The set terminal S of the RS flip-flop U₈ receives the other outputof the oscillator OSC which can include a clock signal. The outputterminal Q of the RS flip-flop U₈ is coupled to the first input terminalof the first OR gate U₆ (i.e., the first input terminal of the secondlogic circuit) and the first input terminal of the second OR gate U₇(i.e., the second input terminal of the second logic circuit). One inputterminal of the adder A₁ receives V_(P′), while the another inputterminal receives V_(N′). The adder A₁ adds the two inputs and sends itsoutput to the non-inverting input terminal of the second operationalamplifier U₂.

The adders A₀ and A₁ can include any desired arithmetic unit to carryout a desired calculation. For example, the output of the adder A₁ canbe β₁*V_(P)+β₂*V_(N′), where β₁, β₂ are coefficients that can be set todifferent values (even negative values) depending on particularity ofeach SIMO circuit. Furthermore, the number of the operational amplifierin control loop 1 is up to the number of the system output. It is two inthis embodiment, thus there are two operational amplifiers U₀ and U₁.

In the illustrated embodiment, the inverting input terminal of thesecond operational amplifier U₂ is grounded, and the output terminal ofthe second operational amplifier U₂ is coupled to the input terminal ofthe absolute circuit ABS and the non-inverting input terminal of thecomparator U₅. The inverting input terminal of the comparator U₅ isgrounded, and the output terminal of the comparator U₅ (i.e., the firstoutput terminal of the switch duty-cycle subtraction control circuit 7)is coupled to the fourth input terminal of the second logic circuit 6,to control the operation of the first switch S₁ and the second switchS₂. The output terminal of the absolute circuit ABS is coupled to thenon-inverting input terminal of the comparator U₄. The inverting inputterminal of the comparator U₄ is coupled to the output terminal G of thecurrent source I_(S) and one terminal of the capacitor C₀. The otherterminal of the capacitor C₀ is grounded. The output terminal G of thecurrent source I_(S) is coupled to one terminal of the switch S₃ aswell. The other terminal of the switch S₃ is grounded. As a result, thecurrent source I_(S), the capacitor C₀, and the switch S₃ form asaw-tooth generator. The falling edge of the saw-tooth signal generatedby the saw-tooth generator is synchronized to the peak value of theinductor current.

As shown in FIG. 3, the output terminal of the comparator U₄ (i.e., thesecond output terminal of the switch duty-cycle difference controlcircuit) is coupled to the joint terminal of the first switch S₁ and thesecond switch S₂ (i.e., the third input terminal of the second logiccircuit). The other terminal of the switch S₁ is coupled to the secondinput terminal of the first NAND gate U₆ and one terminal of the firstresistor R₁. The other terminal of the switch S₂ is coupled to thesecond input terminal of the second NAND gate U₇ and one terminal of thesecond resistor R₂. The output terminal G₁ of the first NAND gate U₆ iscoupled to the gate of the switch M₁ in the SIMO circuit of the system,while the output terminal G₂ of the second NAND gate U₇ is coupled tothe gate of the switch M₂ in the SIMO circuit of the system, to controlthe operation of the switches M₁ and M₂. The other terminal of theresistor R₁ and the other terminal of the resistor R₂ are grounded.

FIG. 4A depicts waveforms of the control circuit when the SIMO circuitis operating according to operation scenario 1 during the secondsub-period. FIG. 4B depicts waveforms of the control circuit when theSIMO circuit is operating according to operation scenario 2 during thesecond sub-period.

At the beginning of each operation cycle, i.e., at time 0, the setterminal S of the RS flip-flop is triggered by the clock signal Cgenerated by the oscillator OSC. Thus the output Q of the RS flip-flopis set high, i.e., the signal D is high. Accordingly, the output G₁ ofthe first NAND gate U₆ and the output G₂ of the second NAND gate U₇ arehigh, causing the switches M₁ and M₂ in the SIMO circuit to be turnedon. The input V_(IN), the switch M₁, the inductor L and the switch M₂form a current loop in the SIMO circuit. The input V_(IN) is supplied tothe inductor L, and the operation enters the first sub-period 0˜t₀.

The adder A₂ adds I_(M) with the saw-tooth signal generated by theoscillator OSC. Then the adder A₂ sends its output to the non-invertinginput terminal of the comparator U₃. The saw-tooth signal may beutilized for slope compensation and/or for other suitable purposes. Theadder A₀ adds the output from the operational amplifier U₀ and theoperational amplifier U₁ to obtain an output signal A. When the currentI_(M) in the switch M₂ continuously increases to cause the output signalof the adder A2 to be greater than the signal A, i.e., at time t₀, theoutput signal B of the comparator U₃ is set high. Because thepeak-current mode is applied to the first control loop, I_(M) begins todecline when it reaches the value of the signal A. Thus, signal B is ashort pulse. Signal B resets the RS flip-flop, namely, it turns theoutput Q of the RS flip-flop to low, i.e., signal D is low. Therefore,the output of the first NAND gate U₆ and the output of the second NANDgate U₇ are determined by the second input signals at their respectivesecond input terminals.

As shown in FIG. 3, the operations of the first switch SI and the secondswitch S₂ are both controlled by signal H. The switch S₁ is turned onwhen signal H is low, and the switch S₂ is turned on when signal H ishigh. Thus, the switch S₁ and the switch S₂ are not turned on at thesame time. Therefore, there is no more than one high-level signalbetween signal G₁ and signal G₂. Thus the system enters the secondsub-period t₀˜t₁. In addition, signal B turns the switch S₃ to on, whichpulls the output G of the current source I_(S) to ground. The chargesacross the capacitor C₀ are discharged immediately, causing the voltagedrop across the capacitor C₀ to be zero.

When the short pulse of the signal B is over, i.e., the level of signalB turns low, the switch S₃ is turned off, causing the current sourceI_(S) to charge the capacitor C₀, thus the voltage across the capacitorC₀ is increased at a slope of I_(S)/C, where C is the capacitance of thecapacitor C₀. Thus the output G of the current source I_(S) can be asaw-tooth signal or other suitable types of signals. Such saw-toothsignal is sent to the inverting input terminal of the comparator U₄. Thecurrent source Is, the capacitor C₀ and the switch S₃ form a saw-toothgenerator. Even though a particular saw-tooth generator is discussedabove, in other embodiments, the saw-tooth generator can have othersuitable components in other desired arrangements.

When the amplitude of V_(P′) is lower than the amplitude of V_(N′), theoutput of the adder A₁ is negative, causing the output signal E of thesecond operational amplifier U₂ and the output signal H of thecomparator U₅ to be negative. The first switch S₁ is turned on and thesecond switch S₂ is turned off due to the low-level signal H, causingthe input terminal of the first NAND gate U₆ to receive the outputsignal I of the comparator U₄, and also causing the second NAND gate U₇to be decoupled from the signal I. The negative signal E becomes apositive signal F via the absolute circuit ABS. When the saw-toothsignal at the inverting input terminal of the comparator U₄ increasesbut is still lower than the signal F, signal I is high, resulting in ahigh-level signal G₁, and the switch M₁ in the SIMO circuit to be turnedon. Moreover, the switch M₂ in the SIMO circuit is turned off, thus thesystem operation enters operation scenario 1 during the secondsub-period: the switch M₁ is turned on, the diode D₁ is freewheeling,the switch M₂ and the diode D₂ are off. Then the input V_(IN) , theswitch M₁, the inductor L, the diode D₁ and the capacitor C₁ form acurrent loop. The inductor current I_(L) is declined linearly at a slopeof (V_(P)−V_(IN))/L, the input V_(IN) and the inductor L are supplied tothe capacitor C₁ to increase the output V_(P), as shown in FIG. 4A.

When the amplitude of V_(P), is higher than the amplitude of V_(N′), theoutput of the adder A₁ is positive, causing signal E and signal H to bepositive. The first switch S₁ is turned off and the second switch S₂ isturned on due to the high-level signal H, causing the input terminal ofthe second NAND gate U₇ to receive signal I, and the first NAND gate U₆to be decoupled from signal I. The positive signal E becomes a positivesignal F via the absolute circuit ABS. When the saw-tooth signal at theinverting input terminal of the comparator U₄ increased but is stilllower than signal F, signal I is high, resulting in a high-level signalG₂, and the switch M₁ in the SIMO circuit to be turned off. Moreover,the switch M₂ in the SIMO circuit is turned on, thus the systemoperation enters case 2 during the second sub-period: the switch M₂ isturned on, the diode D₂ is freewheeling, the switch M₁ and the diode D₁are off. Then the inductor L, the switch M₂, the capacitor C₂ and thediode D₂ form a current loop. The inductor current I_(L) is declinedlinearly at a slope of V_(N)/L, the inductor L is supplied to thecapacitor C₂ to increase the amplitude of the output V_(N), as shown inFIG. 4B.

When the saw-tooth signal G increases to be higher than signal F, i.e.,at time t₁, the output signal of the comparator U₄ is low. No matterwhich switch (either switch S₁ or switch S₂) is turned on, signal G₁ andsignal G₂ are low. Thus the operation enters the third sub-period t₁˜T.The inductor L, the diode D₁, the capacitor C₁, the diode D₂ and thecapacitor C₂ form a current loop. The inductor current I_(L) is declinedlinearly at a slope of (V_(P)−V_(N))/L, the inductor L is supplied tocapacitors C₁, C₂ and the load. At time T, the oscillator OSC outputs anew clock signal C, the SIMO circuit enters a new operation cycle, andrepeats the operation illustrated hereinbefore.

When the SIMO circuit is operating in a discontinuous current mode(DCM), the operation under scenario 1 and 2 are shown in FIG. 2C andFIG. 2D respectively. The operation during the first sub-period and thesecond sub-period are the same as that in CCM. However, after time t₁,the operation entered the third sub-period, at time t₂, the inductorcurrent I_(L) declines to zero, the diodes D₁ and D₂ are no longerfreewheeling. At the same time, switches M₁ and M₂ are turned off, thuscapacitors C₁ and C₂ are supplied to their respective load. At time T,the oscillator OSC outputs a new clock signal C, the SIMO circuit entersa new operation cycle, and repeats the operation illustratedhereinbefore.

During the first sub-period 0˜t₀, switches M₁ and M₂ are both turned on;during the second sub-period t₀˜t₁, one of them is turned on while theother is turned off; during the third sub-period t₁˜T, both of them areturned off. Therefore, the foregoing SIMO circuit uses the algebraicrelations of each output of the SIMO circuit to control the duty-cycleof each switch in order to control each output voltage of the SIMOcircuit. As a result, several embodiments of the SIMO circuit can reducevoltage ripple commonly encountered in conventional circuits.

From the foregoing, it will be appreciated that specific embodiments ofthe invention have been described herein for purposes of illustration,but that various modifications may be made without deviating from theinvention. For example, many of the elements of one embodiment may becombined with other embodiments in addition to or in lieu of theelements of the other embodiments. Accordingly, the invention is notlimited except as by the appended claims.

1. A single inductor multiple output (SIMO) system, comprising: aplurality of output terminals; a plurality of switches operativelycoupled to the output terminals; a first control loop configured tocontrol a peak current in the SIMO system; and a second control loopelectrically coupled to the first control loop, the second control loopbeing configured to control a duty-cycle difference between the switchesto achieve a desired voltage at the individual output terminals.
 2. TheSIMO system of claim 1, wherein the first control loop comprises: apeak-current control value setting circuit configured to receivemultiple sensed output of the SIMO system; a slope signal generatorconfigured to provide a slope signal and a clock signal; an adderconfigured to receive a sensed current of the SIMO system at one inputterminal and to receive the slope signal at another input terminal; afirst comparator configured to receive the output of the peak-currentvalue setting circuit at one input terminal, and to receive the outputof the adder at another input terminal; a first logic circuit configuredto receive the output of the first comparator at one input terminal, andto receive the clock signal at another input terminal; and a secondlogic circuit configured to receive a first output of the second controlloop at a first input terminal, to receive a second output of the secondcontrol loop at a second input terminal, to receive the output of thefirst logic circuit at a third input terminal, and to provide multiplecontrol signals to control terminals of the multiple switches,respectively.
 3. The SIMO system of claim 1, wherein the second controlloop comprises a switch duty-cycle difference control circuit configuredto receive the multiple sensed output of the SIMO system at multipleinput terminals, respectively.
 4. The SIMO system of claim 2, whereinthe peak-current control value setting circuit comprises: a plurality ofoperational amplifiers, wherein each operational amplifier is configuredto receive a sensed output voltage of the SIMO system at one inputterminal and to receive a corresponding reference voltage level atanother input terminal; and a first arithmetic unit configured toreceive the output of each operational amplifier at multiple inputterminals, and to provide an output of the peak-current control valuesetting circuit to one input terminal of the first comparator.
 5. TheSIMO system of claim 4, wherein a number of the operational amplifiersis based at least in part on a number of output terminals in the SIMOsystem.
 6. The SIMO system of claim 2, wherein the slope signalgenerator is an oscillator.
 7. The SIMO system of claim 2, wherein thefirst logic circuit is a RS flip-flop.
 8. The SIMO system of claim 2,wherein the second logic circuit comprises a first OR gate, a second ORgate, a first resistor, a second resistor, a first switch, and a secondswitch.
 9. The SIMO system of claim 3, wherein the switch duty-cycledifference control circuit comprises: a second arithmetic unit havingmultiple input terminals; a second operational amplifier configured toreceive the output of the second arithmetic unit at one input terminal,while the other input terminal of the second operational amplifier isgrounded; an absolute value circuit configured to receive the output ofthe second operational amplifier; a second comparator configured toreceive the output of the absolute value circuit at one input terminal,to receive a saw-tooth wave signal at another input terminal, and toprovide the first output of the second control loop; a third comparatorconfigured to receive the output of the second operational amplifier atone input terminal with the other input terminal of the secondcomparator grounded; and a saw-tooth generator configured to receive theoutput of the first comparator and to provide a saw-tooth signal. 10.The SIMO system of claim 9, wherein the saw-tooth generator comprises acurrent source, a capacitor, and a switch configured to generate thesaw-tooth signal.
 11. The SIMO system of claim 9, wherein a falling edgeof the saw-tooth signal generated by the saw-tooth generator issynchronized to the peak current of the SIMO system.
 12. A method ofconverting a signal input signal into multiple output signals,comprising: supplying power to a plurality of output terminals based ona signal input signal; detecting a voltage at individual outputterminals; determining an arithmetic relationship between the detectedvoltages of the output terminals; and adjusting the power supplied tothe plurality of output terminals based at least in part on thedetermined arithmetic relationship between the detected voltages of theoutput terminals.
 13. The method of claim 12, wherein determining anarithmetic relationship includes summing detected voltages.
 14. Themethod of claim 12, wherein supplying power includes supplying power viaan inductor, and wherein the method further includes adjusting a peakcurrent of the inductor to achieve a desired voltage at the plurality ofoutput terminals.
 15. The method of claim 12, wherein supplying powerincludes controlling the supplied power using a plurality of switchesindividually having a duty cycle, and adjusting the power suppliedincludes adjusting a difference of the duty-cycles of the switches basedat least in part on the determined arithmetic relationship between thedetected voltages of the output terminals.